Fast transient transistor simulation programs are important aids in computer aided design (CAD) of very large scale integrated (VLSI) circuits. A fast transient simulator differs from accurate circuit simulators like SPICE in its ability to simulate very large circuits at significantly higher speed, at the expense of some accuracy. Fast transient simulators provide the ability to simulate at transistor level circuits containing hundreds of thousands of transistors with high speed on the orders of hundreds time faster than accurate circuit simulators such as SPICE. The goal of fast transient simulators is to compute waveforms of voltages at circuit nodes and currents through circuit elements. Fast transient simulators are used when it is required to simulate circuits at an accuracy higher than that can be achieved by gate and switch level simulators, and with a speed higher than SPICE-like simulators.
Fast transient simulation of a Metal Oxide Semiconductor (MOS) transistor circuit usually partitions the given circuit into D.C. connected components (DCCC). Each MOSFET model is cut across its transistor gate. The interaction between partitions is simplified by considering only the dependence of MOSFET channel current on its gate voltage. Each partition is simulated independently for a short time interval called the time step. During this time interval, it is assumed that all voltages at the boundary nodes of the partition are known. Usually they are computed through linear approximation, by interpolation and extrapolation. Based on such simplifications, the behavior of each partition is simulated independently for some short time interval called a time step. Time steps can be different for different partitions and they can vary during simulation for getting the desired trade-off between speed and accuracy. The partitions that do not change their state or change it slowly are evaluated with much longer time steps. This technique improves simulation speed as compared to traditional transistor level circuit simulators like SPICE. Because of the partition mechanism and the use of different time steps, the time points at which the simulator recomputes the states of the partitions are different for each partition. The simulator arranges reevaluation of partition states in an event driven manner. The simulator plans reevaluations of partition states according to its internal processes and changes of voltages at the partition boundary. For this purpose, it uses an event queue where it schedules partitions for reevaluation. From this queue, the simulator gets partitions for reevaluation according to their time schedule.
The accurate behavior of each partition is described by a system of non-linear differential equations. One of the most accurate techniques to simulate the behavior of non-linear circuits is to use a modified nodal analysis for computing the system of equations, trapezoidal or backward Euler integration algorithm for their numerical integration, and Newton-Raphson iterations for computing voltage and current values at each time point. Such an approach is common for implementing accurate circuit simulators like SPICE. In order to get higher simulation speed, this technique is simplified in many ways. For example, the forward Euler integration algorithm can be applied, or the Newton-Raphson iterations can be substituted by approximate linearization of non-linear elements at each time point. Any type of simplification is at the cost of accuracy of the simulation results. Fast simulators differ among themselves in their selection of trade-off between speed and accuracy.
For simulating partitions, fast circuit simulators similar to traditional SPICE-like circuit simulators require a model of MOS transistors. For SPICE simulators, an accurate transistor model is specified by very complex formulae for computing currents and charges of each transistor terminal as a function of terminal voltages. Computation of these complex formulae significantly slows down circuit simulation. In order to have high simulation speed, fast transient circuit simulators usually use a simplified transistor model. The simplified transistor model can be either analytical or table-based. Analytical models are usually not accurate enough for submicron short channel MOS transistors. Table models usually are able to provide much higher accuracy with higher computation speed. In the simplest straight forward approach, a table model is a collection of tables, each of which provides values of transistor terminal currents or charges as functions of terminal voltages. The tables are usually computed by using an accurate transistor level simulator like SPICE.
The structure of a conventional bulk MOS transistor 10 is shown in FIG. 1. Transistor 10 has a substrate 12, a gate oxide 14, a gate 16, a drain 17 and a source 18. The electrical model 34 of transistor 10 is shown in FIG. 2 and has four terminals: a drain 37, a source 38, a gate 36 and a substrate 39. Therefore, a straight-forward model approach results in four charge tables and four current tables. Each of the tables has four arguments or inputs, viz. the four terminal voltages. Unfortunately, tables organized in such a manner are too large to use efficiently in any simulator. Therefore, fast transient simulators use different techniques to simplify their table models. The first simplification comes from the fact that transistor behavior does not change if we change all terminal voltages by the same value. In other words, transistor behavior is invariant to voltage shift. This simplification allows a reduction in the number of table arguments by one as one of the four terminals can be treated as a reference terminal. Other facts that are used for model simplification are charge and current conservation laws. The conservation laws make it sufficient to have models only for three terminal currents and charges and allow computation of the current and charge of the fourth terminal so that total charge and current ate zero. Unfortunately, these simplifications are not enough to make transistor models sufficiently efficient. Therefore, fast transient circuit simulators often use additional approximations for simplifying a transistor table model. For bulk MOS transistors, it is common to assume that transistor terminal capacitances are linear, meaning that they do not depend on transistor terminal voltages. This assumption permits using just average values of transistor terminal capacitances instead of a table of terminal charges as functions of terminal voltages. Currents of bulk MOS transistor table models can be simplified by ignoring substrate and gate currents as they are orders of magnitude less than transistor channel current and do not affect circuit behavior drastically. Simulators can simplify the model of bulk transistor channel current by considering the channel current as a function of two variables: (1) the voltage between drain and source and (2) the effective gate voltage. The effective gate voltage is defined as a difference between gate-to-source voltage and a threshold voltage, predetermined for each transistor. Threshold voltage is considered as a function of body voltage and may be modeled by a separate one-dimensional table. This approach follows from the simple analytical model of a bulk MOS transistor. Thus, instead of one three-dimension table for channel current, two smaller tables are used: one two-dimensional table and one single-dimensional table. Such table reduction costs some accuracy of the model. For pure digital MOS circuits, especially for CMOS circuits, the foresaid reduction still retains sufficient accuracy and allows the simulator to compute good approximation of circuit delays and power consumption. However, this model is not accurate enough for many circuits, for example circuits using many pass gates, circuits having very large D.C. connected components, and circuits that are very sensitive to accuracy, such as the PLL (Phase Locked Loop) circuits.
Additional challenge and problem for fast circuit simulation are SOI circuits that are becoming more and more popular in high speed and low power VLSI designs. The structure of an SOI MOS transistor 20 is shown in FIG. 3. An SOI transistor is similar to a bulk transistor but it is manufactured on an insulator layer and completely isolated from one to another by the same insulator. SOI transistor 20 has a substrate (backgate) 22, a buried oxide 24, a body 26, a gate oxide 27, a gate 28, a source 29, a drain 30 and a shallow trench isolation 32 around the perimeter. Because of the SOI structure, transistor capacitances are much smaller than the ones in a comparable size bulk transistor. The reduced capacitances make an SOI transistor significantly faster and reduce power consumption. Thus SOI transistors are very attractive for high performance and low power circuits. SOI transistors also have other benefits like latch-up immunity, lower radiation susceptibility, etc. Unfortunately, designing VLSI circuits with SOI transistors is more difficult than with bulk transistors because SOI transistors have more complicated behavior than bulk transistors. In bulk transistors, the fourth terminal is a VLSI substrate that is permanently connected to ground or a supply voltage VDD. The counterpart terminal in an SOI transistor is a body that has very small capacitance and usually is not connected to any other circuit node. Because of that, the body potential (voltage) varies significantly during circuit operation due to such effects like capacitive coupling with other circuit nodes, leakage, and impact ionization currents. These effects significantly influence SOI transistor behavior by changing its threshold voltage.
Another complication with the SOI transistor model arises due to its usage with different types of body connections. The most common case, and also the most difficult to simulate, is the floating body configuration wherein the transistor body is not connected to any other circuit node. The floating body type SOI transistor configuration provides the smallest transistor area but makes its behavior less predictable. The potential of a floating body can vary due to variation in the switching frequency, thus giving rise to an effect known as the history effect. This effect makes logic gate delay depend on gate switching history. Another type of SOI MOSFET configuration has its body and source connected together that makes its behavior similar to a bulk MOS transistor. An example of this configuration is illustrated in FIG. 4 wherein a structure 50 has an SOI transistor having an n+ drain 52, a gate 54, an n+ source 56 and a p+ tie 58 to tie the body with the source 56. The third type of SOI transistor configuration has a separate body contact that can be connected to any node of the circuit. An example of this configuration is illustrated in FIG. 5 wherein a structure 60 has an SOI transistor having an n+ drain 62, an n+ source 64, a gate 66 and a p+ body contact 68. Thus, transient simulators of SOI circuits should handle all these three types of transistors.
The electrical model of an SOI transistor is shown in FIG. 6. SOI transistor 40 has five terminals as compared to four terminals of a bulk MOS transistor. Transistor 40 has a gate 42, a drain 44, a source 45, a body 46 and a backgate (substrate) 48. The additional terminal makes an SOI model significantly more complex and results in significant increase in model's table size.
Simulation of SOI circuits is more sensitive to numerical errors because the history effect has a very large characteristic time constant as compared to logic gates' switching time. Even small numerical errors in body charge computation are accumulated resulting in prediction of wrong circuit delays. Because of that, accurate transient circuit simulators simulate SOI circuits much slower than bulk circuits that makes circuit design with SOI transistors even more difficult.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.